1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
In this specification, a semiconductor device means all devices which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and an electronic device are all semiconductor devices.
2. Description of the Related Art
A metal oxide silicon field-effect transistor (MOSFET), which is formed over a silicon substrate, has been applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (display device).
The operation speed and integration degree of a MOSFET are improved by miniaturization in accordance with the scaling law as follows: reduction in the size of a MOSFET to 1/k increases its speed k times and reduces its electric power to 1/k2. In this manner, reduction in the channel length and reduction in the thickness of a gate insulating film of a MOSFET have been achieved.
With the reduction in the channel length of a MOSFET, however, deterioration in electric characteristics becomes pronounced, that is, a problem of a short-channel effect occurs.
An example of the short-channel effects is deterioration in electric characteristics due to a punch-through phenomenon. The punch-through phenomenon is a phenomenon in which an electric field on the drain side adversely affects a diffusion potential on the source side and decreases it, and a current flows between the source and the drain even in the state where a channel is not formed. In other words, a depletion layer on the drain side extends to the source and produces, on the source, an effect of the electric field on the drain side.
Another example of the short-channel effects is deterioration in electric characteristics due to hot carriers. Hot carriers generated by application of high electric field to the vicinity of a drain region have energy large enough to pass an oxide film such as a gate insulating film, and part of the hot carriers causes deterioration, such as change (shift) in threshold voltage, increase in sub-threshold value (S value), or increase in leakage current in a transistor, by being captured in the gate insulating film or by forming an interface level.
In addition, injection of a carrier generated due to collisional ionization or avalanche breakdown into an oxide film as a hot carrier (such a carrier is called drain avalanche hot carrier: DAHC) and injection of a hot carrier generated due to the second collisional ionization (such a carrier is called secondarily generated hot electron: SGHE) also cause deterioration in electric characteristics of a transistor.
To suppress such a short-channel effect of a MOS transistor, reduction in thickness of a gate insulating film has been attempted. With a thin gate insulating film, the gate electrode layer can be close to a channel region, and thus influence of the gate electrode layer on the channel region is enhanced, which can suppress the above short-channel effect. Accordingly, reduction in the thickness of the gate insulating film, which improves the operation speed and integration degree of a MOSFET and suppresses a short-channel effect of the MOSFET, has been used as an effective technique for the MOSFET.
However, reduction in the thickness of the gate insulating film (3 nm or less, for example) causes a problem of a tunnel current passing through the gate insulating film. To solve this problem, study in which instead of silicon oxide, a high-k material (e.g., hafnium oxide), which has a higher permittivity than silicon oxide, is used as a material of the gate insulating film has been conducted (e.g., see Patent Documents 1 and 2). With the use of a high-k material, effective thickness for silicon oxide (equivalent oxide thickness (EDT) which is obtained by convertion into a film thickness of silicon oxide) of the gate insulating film can be reduced (to 3 nm or less, for example) while the physical thickness thereof can be large enough to prevent a tunnel current.
Furthermore, some measures for preventing a short-channel effect of a MOSFET including a silicon semiconductor have been needed; for example, a special impurity region (such a region is called a pinning region) is formed in a channel formation region (e.g., see Patent Document 3).
Furthermore, as a means for preventing deterioration of a MOS transistor due to hot carriers, a structure having a region where an impurity element is added at a low concentration (hereinafter also referred to as LDD (lightly doped drain) region) between a channel formation region and a source or drain region has been known (for example, see Patent Document 4). Since an electric field in the vicinity of the drain region is increased as the distribution of an impurity concentration at a junction between the drain region and a channel region is steeper, the formation of such an LDD region between the drain region and the channel region can reduce electric-field concentration and relieve a hot carrier effect. On the other hand, the formation of the LDD region increases the diffusive resistance in a drain part, which leads to decrease in switching speed of a transistor; or the formation of the LDD region increases series resistance in the drain part, which leads to decrease in on-state current of the transistor. Furthermore, a transistor increases in its size by an area of the LDD region, which runs counter to a demand for miniaturization of a transistor.